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Release 1.0, 1 July 2002 F. Chapter P Error Handling
187
58
16
30
16
DMMU_TAG_ACCESS RW Parity LDXA #D
IUG_TSBP
W (WotherD)
58
16
38
16
DMMU_VA_WATCHPOINT RW Parity Enabled
LDXA
(I)AUG_CRE
I(A)UG_CRE
W
W
58
16
40
16
DMMU_PA_WATCHPOINT RW Parity Enabled
LDXA
(I)AUG_CRE
I(A)UG_CRE
W
W
58
16
48
16
DMMU_TSB_PEXT RW Parity = DTSB_BASE
I(A)UG_TSBCTXT
W
58
16
50
16
DMMU_TSB_SEXT RW Parity = DTSB_BASE
I(A)UG_TSBCTXT
W
58
16
58
16
DMMU_TSB_NEXT RParity= DTSB_BASE
I(A)UG_TSBCTXT
None
59
16
— DMMU_TSB_8KB_PTR RPPLDXA
IUG_TSBP
WotherD
5A
16
— DMMU_TSB_64KB_PTR RPPLDXA
IUG_TSBP
WotherD
5B
16
— DMMU_TSB_DIRECT_PTR RPPLDXA
IUG_TSBP
WotherD
5C
16
— DTLB_DATA_IN WParityDTLB write
IUG_DTLB
DemapAll
5D
16
— DTLB_DATA_ACCESS RW Parity LDXA
DTLB write
IUG_DTLB
IUG_DTLB
DemapAll
DemapAll
5E
16
— DTLB_TAG_READ RParityLDXA
IUG_DTLB
DemapAll
5F
16
— DMMU_DEMAP WParityDTLB write
IUG_DTLB
DemapAll
60
16
— IIU_INST_TRAP RW Parity LDXA No match at error W
6E
16
00
16
EIDR RW Parity Always
IAUG_CRE
W
6F
16
— parallel barrier assist RW Parity
AUG
always
LDXA
BV interface
Not detected (#dv)
COREERROR
(#dv)
(I)AUG_CRE
W
W
None
77
16
40
16
–
88
16
INTR_DATA0:7_W
INTR_DISPATCH_W
W
W
Gecc
Gecc
None
store
—
(I)AUG_CRE
W
W
7F
16
40
16
–
88
16
INTR_DATA0:7_R RECCLDXA
intr_receive
COREERROR
(#dv)
BUSY =0
Interrupt
Receive
EF
16
— Parallel barrier assist RW Parity
AUG
always
LDXA
BV interface
Not detected (#dv)
COREERROR
(#dv)
(I)AUG_CRE
W
W
None
TABLE P-20
Handling of ASI Register Errors (Continued)
ASI VA
Register Name RW
Error
Protect
Error Detect
Condition Error Type Correction