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208 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Q.2.4 Cache Event Counters
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I1 Cache Miss Count (if_r_iu_req_mi_go)
Counts the occurrences of I1 cache misses.
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D1 Cache Miss Count (op_r_iu_req_mi_go)
Counts the occurrences of D1 cache misses.
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I1 Cache Miss Latency (if_wait_all)
Counts the total latency of I1 cache misses.
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D1 Cache Miss Latency (op_wait_all)
Counts the total latency of D1 cache misses.
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L2 Cache Miss Wait Cycle by Demand Access
(sx_miss_wait_dm)
Counts the number of cycles from the occurrence of an L2 cache miss to data
returned, caused by demand access.
●
L2 Cache Miss Wait Cycle by Prefetch (sx_miss_wait_pf)
Counts the number of cycles from the occurrence of an L2 cache miss to data
returned, caused by both software prefetch and hardware prefetch access.
Counter picu2
Encoding 100000
2
Counter picl2
Encoding 100000
2
Counter picu3
Encoding 100000
2
Counter picl3
Encoding 100000
2
Counter picu0
Encoding 110000
2
Counter picl0
Encoding 110000
2