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4 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
■
Asynchronous data error (
ADE
) trap for additional errors:
■
Relaxed instruction end method (precise, retryable, not retryable) for the
async_data_error
exception to indicate how the instruction should end; depends
on the executing instruction and the detected error.
■
Some
ADE
traps that are deferred but retryable.
■
Simultaneous reporting of all detected
ADE
errors at the error barrier for correct
handling of retryability.
1.3.1 Component Overview
The SPARC64 V processor contains these components.
■
Instruction control Unit (IU)
■
Execution Unit (EU)
■
Storage Unit (SU)
■
Secondary cache and eXternal access Unit (SXU)
FIGURE 1-1
illustrates the major units; the following subsections describe them.