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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
When a parity error is detected in an
ITLB
entry when an
LDXA
instruction attempts
to read
ASI_ITLB_DATA_ACCESS
or
ASI_ITLB_TAG_ACCESS
, hardware
automatically demaps the entry and an instruction urgent error is indicated in
ASI_UGESR.IUG_ITLB
.
Error in sTLB Entry Detected During Virtual Address
Translation
When a parity error is detected in the
sTLB
entry during a virtual address
translation, hardware automatically demaps the entry and does not report the error
to software.
Error in fTLB Entry Detected During Virtual Address
Translation
When an fTLB tag has a parity error, the fTLB entry never matches any virtual
address. An fTLB tag error in a locked entry causes a TLB miss for the virtual
address already registered as the locked TLB entry.
A parity error in fTLB entry data is detected only when the tag of the fTLB entry
matches a virtual address.
When a parity error in the fITLB is detected at the time of an instruction fetch, a
precise
instruction_access_error
exception is generated. The parity error in the
fITLB
entry and the
fITLB
entry index is indicated in
ASI_IFSR
.
When a parity error in
fDTLB
is detected for the memory access of a load or store
instruction, a precise
data_access_error
exception is generated. The parity error in the
fDTLB
entry and the
fDTLB
entry index is indicated in
ASI_DFSR
.
P.10.2 Automatic Way Reduction of sTLB
When frequent errors occur in
sITLB
and
sDTLB
, hardware automatically detects
that condition and reduces the way, with no adverse effects on software.
Way Reduction Condition
Hardware counts
TLB
entry parity error occurrences for each
sITLB
way and
sDTLB
way. If the error count per unit of time exceeds a predefined threshold, hardware
recognizes an
sTLB
way reduction condition.