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36 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
7.1.1 RED_state
RED_state Trap Table
The RED_state trap vector is located at an implementation-dependent address
referred to as RSTVaddr. The value of RSTVaddr is a constant within each
implementation; in SPARC64 V this virtual address is FFFF FFFF F000 0000
16
,
which translates to physical address 0000 07FF F000 0000
16
in RED_state (impl.
dep. #114).
RED_state Execution Environment
In RED_state, the processor is forced to execute in a restricted environment by
overriding the values of some processor controls and state registers.
Note –
The values are overridden, not set, allowing them to be switched atomically.
SPARC64 V has the following implementation-dependent behavior in RED_state
(impl. dep. #115):
■
While in RED_state, all internal ITLB-based translation functions are disabled.
DTLB-based translations are disabled upon entry but may be reenabled by
software while in RED_state. However, ASI-based access functions to the TLBs
are still available.
■
While mTLBs and uTLBs are disabled, all accesses are assumed to be
noncacheable and strongly ordered for data access.
■
XIR errors are not masked and can cause a trap.
Note –
When RED_state is entered because of component failures, the handler
should attempt to recover from potentially catastrophic error conditions or to disable
the failing components. When RED_state is entered after a reset, the software
should create the environment necessary to restore the system to a running state.
7.1.2 error_state
The processor enters error_state when a trap occurs while the processor is
already at its maximum supported trap level (that is, when TL = MAXTL) (impl. dep.
#39).