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Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 47
A.4 Block Load and Store Instructions (VIS I)
The following notes summarize behavior of block load/store instructions in
SPARC64 V.
1. Block load and store operations are not atomic, in that they are internally
decomposed into eight independent, 8-byte load/store operations in SPARC64 V.
Each load/store is always issued and performed in the RMO memory model and
obeys all prior MEMBAR and atomic instruction-imposed ordering constraints.
2. Block load/store instructions are out of the scope of V9 memory models, meaning
that self-consistency of memory reference instruction is not always maintained if
block load/store instructions are involved in the execution flow. The following
table describes the implemented ordering constraints for block load/store
instructions with respect to the other memory reference instructions with an
operand address conflict in SPARC64 V:
To maintain the memory ordering even for the memory address conflicts, MEMBAR
instructions shall be inserted into appropriate location in the program.
Although self-consistency with respect to the block load/store and the other
memory reference instructions is not maintained in some cases, register conflicts
between the other instructions and block load/store instructions are maintained
in SPARC64 V. The read-after-write, write-after-read, and write-after-write
obstructions between a block load/store instruction and the other arithmetic
instructions are detected and handled appropriately.
3. Block load instruction operate on the cache if the operand is present.
Program Order for conflicting bld/bst/ld/st
Ordered/
Out-of-Orderfirst next
store blockstore Ordered
store blockload Ordered
load blockstore Ordered
load blockload Ordered
blockstore store Out-of-Order
blockstore load Out-of-Order
blockstore blockstore Out-of-Order
blockstore blockload Out-of-Order
blockload store Ordered
blockload load Ordered
blockload blockstore Ordered
blockload blockload Ordered