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Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 105
F.11.10 TLB Replacement Policy
Automatic TLB Replacement Rule
On an automatic replacement write to the TLB, the MMU picks the entry to write
according to the following rules:
1. If the following conditions are satisfied—
■
the new entry maps to an 8-Kbyte or an 4-Mbyte unlocked page
■
and ASI_MCNTRL.fw_fITLB = 0 for IMMU automatic replacement
■
and ASI_MCNTRL.fw_fDTLB =0 for DMMU automatic replacement
—then the replacement is directed to the sTLB (2-way TLB). Otherwise, the
replacement occurs in the fully associative TLB (fTLB).
2. If replacement is directed to the 2-way TLB, then the replacement set index is
generated from the TLB Tag Access Register: bits 21:13, bits 30:22 or bits 29:22
depending on the page size and MCNTL.RMD for both I-MMU and D-MMU.
3. If replacement is directed to the fully associative TLB (fTLB), then the following
alternatives are evaluated:
a. The first invalid entry is replaced (measuring from entry 0). If there is no
invalid entry, then
b. the first unused, unlocked (LRU, but clear) entry will be replaced (measuring
from entry 0). If there is no unused unlocked entry, then
c. all used bits are reset, and the process is repeated from Step 3b.
If fTLB is the target of the automatic replacement and all entries in the fTLB have
their lock bit set, the automatic replacement operation is ignored and the entries
in the target fTLB remain unchanged.
Restriction of sTLB Entry Direct Replacement
On SPARC64 V, direct replacement of a specific sTLB entry requires that the stxa
instruction to the I/D TLB Data Access Register be designated as follows.
■
stxa ASI designation:
■
ASI 55
16
for sITLB
■
ASI 5D
16
for sDTLB
■
stxa virtual address designation:
■
VA<17:16> = 10
02
: sTLB designation
■
VA<15> = 0 or 1 : Error injection designation
■
VA<13> = 0 or 1 : 8-Kbyte or 4-Mbyte page designation
■
VA<12> = 0 or 1 : sTLB way number
■
VA<11:3> : sTLB index number