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10 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
instruction retired Term applied to an instruction when all machine resources (serial numbers,
renamed registers) have been reclaimed and are available for use by other
instructions. An instruction can only be retired after it has been committed.
instruction stall Term applied to an instruction that is not allowed to be issued. Not every
instruction can be issued in a given cycle. The SPARC64 V implementation
imposes certain issue constraints based on resource availability and program
requirements.
issue-stalling
instruction An instruction that prevents new instructions from being issued until it has
committed.
machine sync The state of a machine when all previously executing instructions have
committed; that is, when no issued but uncommitted instructions are in the
machine.
Memory Management
Unit (MMU) Refers to the address translation hardware in SPARC64 V that translates 64-bit
virtual address into physical address. The MMU is composed of the mITLB,
mDTLB, uITLB, uDTLB, and the ASI registers used to manage address
translation.
mTLB Main TLB. Split into I and D, called mITLB and mDTLB, respectively. Contains
address translations for the uITLB and uDTLB. When the uITLB or uDTLB do
not contain a translation, they ask the mTLB for the translation. If the mTLB
contains the translation, it sends the translation to the respective uTLB. If the
mTLB does not contain the translation, it generates a fast access exception to a
software translation trap handler, which will load the translation information
(TTE) into the mTLB and retry the access. See also TLB.
uDTLB Micro Data TLB. A small, fully associative buffer that contains address
translations for data accesses. Misses in the uDTLB are handled by the mTLB.
uITLB Micro Instruction TLB. A small, fully associative buffer that contains address
translations for instruction accesses. Misses in the uTLB are handled by the
mTLB.
nonspeculative A distribution system whereby a result is guaranteed known correct or an
operand state is known to be valid. SPARC64 V employs speculative
distribution, meaning that results can be distributed from functional units
before the point at which guaranteed validity of the result is known.
reclaimed The status when all instruction-related resources that were held until commit
have been released and are available for subsequent instructions. Instruction
resources are usually reclaimed a few cycles after they are committed.
rename registers A large set of hardware registers implemented by SPARC64 V that are invisible
to the programmer. Before instructions are issued, source and destination
registers are mapped onto this set of rename registers. This allows instructions
that normally would be blocked, waiting for an architected register, to proceed