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34 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Execution Stages for Cache Access
Memory access requests are passed to the cache access pipeline after the target
address is calculated. Cache access stages work the same way as instruction fetch
stages, except for the handling of branch prediction. See Section 6.4.1, Instruction
Fetch Stages, for details. Stages in instruction fetch and cache access correspond as
follows:
When an exception is signalled, fetch ports and store ports used by memory access
instructions are released. The cache access pipeline itself remains working in order to
complete outgoing memory accesses. When data is returned, it is then stored to the
cache.
6.4.4 Completion Stages
■
U (Update) — Update of physical (renamed) register.
■
W (Write) — Update of architectural registers and retire; exception handling.
■
After an out-of-order execution, execution reverts to program order to complete.
Exception handling is done in the completion stages. Exceptions occurring in
execution stages are not handled immediately but are signalled when the
instruction is completed.
1
Instruction Fetch Stages Cache Access
IA Ps
IT Ts
IM Ms
IB Bs
IR Rs
1.RAS-related exception may be signalled before completion.