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42 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
8.1 Overview
Note –
The words “hardware memory model” denote the underlying hardware
memory models as differentiated from the “SPARC V9 memory model,” which is the
memory model the programmer selects in PSTATE.MM.
SPARC64 V supports only one mode of memory handling to guarantee correct
operation under any of the three SPARC V9 memory ordering models (impl. dep.
#113):
■
Total Store Order — All loads are ordered with respect to loads, and all stores are
ordered with respect to loads and stores. This behavior is a superset of the
requirements for the SPARC V9 memory models TSO, PSO, and RMO. When
PSTATE.MM selects TSO or PSO, SPARC64 V operates in this mode. Since
programs written for PSO (or RMO) will always work if run under Total Store
Order, this behavior is safe but does not take advantage of the reduced restrictions
of PSO.
8.4 SPARC V9 Memory Model
Please refer to Section 8.4 of Commonality.
In addition, this section describes SPARC64 V-specific details about the processor/
memory interface model.
8.4.5 Mode Control
SPARC64 V implements Total Store Ordering for all PSTATE.MM. Writing 11
2
into
PSTATE.MM also causes the machine to use TSO (impl. dep. #119). However, the
encoding 11
2
should not be used, since future version of SPARC64 V may use this
encoding for a new memory model.
8.4.6 Synchronizing Instruction and Data Memory
All caches in a SPARC64 V-based system (uniprocessor or multiprocessor) have a
unified cache consistency protocol and implement strong coherence between
instruction and data caches. Writes to any data cache cause invalidations to the