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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-23
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Figure 4-16 Memory Model Feature Register 1 format
Table 4-11 shows how the bit values correspond with the Memory Model Feature Register 1
functions.
To access the Memory Model Feature Register 1 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 5 ; Read Memory Model Feature Register 1.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
L1 test clean operations
L1 cache maintenance operations (unified)
L1 cache maintenance operations (Harvard)
L1 cache line maintenance operations - Set and Way (unified)
L1 cache line maintenance operations - Set and Way (Harvard)
L1 cache line maintenance operations - MVA (unified)
L1 cache line maintenance operations - MVA (Harvard)
Branch predictor
Table 4-11 Memory Model Feature Register 1 bit functions
Bits Field Function
[31:28] Branch predictor Indicates Branch Predictor management requirements.
0x0
, no MMU present.
[27:24] L1 test clean operations Indicates support for test and clean operations on data cache, Harvard or unified
architecture.
0x0
, no support.
[23:20] L1 cache maintenance
operations (unified)
Indicates support for L1 cache, entire cache maintenance operations, unified
architecture.
0x0
, no support.
[19:16] L1 cache maintenance
operations (Harvard)
Indicates support for L1 cache, entire cache maintenance operations, Harvard
architecture.
0x0
, no support.
[15:12] L1 cache line maintenance
operations - Set and Way
(unified)
Indicates support for L1 cache line maintenance operations by Set and Way,
unified architecture.
0x0
, no support.
[11:8] L1 cache line maintenance
operations - Set and Way
(Harvard)
Indicates support for L1 cache line maintenance operations by Set and Way,
Harvard architecture.
0x0
, no support.
[7:4] L1 cache line maintenance
operations - MVA (unified)
Indicates support for L1 cache line maintenance operations by address, unified
architecture.
0x0
, no support.
[3:0] L1 cache line maintenance
operations - MVA (Harvard)
Indicates support for L1 cache line maintenance operations by address, Harvard
architecture.
0x0
, no support.