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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-47
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Figure 4-32 Instruction Fault Status Register format
Table 4-29 shows how the bit values correspond with the Instruction Fault Status Register
functions.
To access the IFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 1 ; Read Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 1 ; Write Instruction Fault Status Register
c5, Auxiliary Fault Status Registers
There are two auxiliary fault status registers:
• the Auxiliary Data Fault Status Register (ADFSR)
• the Auxiliary Instruction Fault Status Register (AIFSR).
These registers provide additional information about data and instruction parity, ECC, and
external TCM errors.
The auxiliary fault status registers are:
• read/write registers
• accessible in Privileged mode only.
Figure 4-33 on page 4-48 shows the bit arrangement in the auxiliary fault status registers.
SReserved
31 30
StatusDomain
4
910111213
Reserved
SD
87
Reserved
Table 4-29 Instruction Fault Status Register bit functions
Bits Field Function
[31:13] Reserved SBZ.
[12] SD Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for
external aborts. For all other aborts types of abort, this bit is set to zero:
0 = AXI Decode error (DECERR) caused the abort
1 = AXI Slave error (SLVERR) caused the abort.
[11] Reserved SBZ.
[10]
a
S Part of the Status field.
[9:8] Reserved SBZ.
[7:4] Domain SBZ. This is because domains are not implemented in this processor.
[3:0]
a
Status Indicates the type of fault generated. To determine the instruction fault, bit [12] and bit [10] must
be used in conjunction with bits [3:0].
a. For more information on how these bits are used in reporting faults, see Table 4-27 on page 4-45.