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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-48
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Precise Data abort
When a precise Data Abort occurs in debug state, the behavior of the processor is
as follows:
• PC, CPSR, SPSR_abt, and R14_abt are unchanged
• the processor remains in debug state
• DSCR[6], sticky precise data abort bit, is set
• DFSR and DFAR are set to the same values as if the abort had occurred in
normal state.
Imprecise Data Abort
When an imprecise Data Abort occurs in debug state, the behavior of the
processor is as follows, regardless of the setting of the CPSR A bit:
• PC, CPSR, SPSR_abt, and R14_abt are unchanged
• the processor remains in debug state
• DSCR[7], sticky imprecise data abort bit, is set
• the imprecise Data Abort does not cause the processor to perform an
exception entry sequence so DFSR remains unchanged
• the processor does not act on this imprecise Data Abort on exit from the
debug state, that is, the imprecise abort is discarded.
Imprecise Data Aborts on entry and exit from debug state
On entering debug state, the processor executes a Data Synchronization Barrier (DSB)
sequence to ensure that any outstanding imprecise Data Aborts are detected, before starting
debug operations.
If the DSB operation detects an imprecise Data Abort, the processor records this event and its
type as if the CPSR A bit was set. The purpose of latching this event is to ensure that it can be
taken on exit from the debug state.
Before forcing the processor to leave debug state, the debugger must execute a DSB sequence
to ensure that all debugger-generated imprecise Data Aborts are detected, and therefore
discarded, while still in debug state. After exiting debug state, the processor acts on any
previously recorded imprecise Data Aborts if permitted by the CPSR A bit.
11.8.11 Leaving debug state
The debugger can force the processor to leave debug state:
• by setting the restart request bit, DRCR[1], to 1
• through the Cross Trigger Interface (CTI) external restart request mechanism.
When one of those restart requests occurs, the processor:
1. Clears the DSCR[1] core restarted flag.
2. Leaves debug state.
3. Clears the DSCR[0] core halted flag.
4. Drives the DBGACK signal LOW, unless the DSCR[11] DbgAck bit is set to 1.
5. Starts executing instructions from the address last written to the PC in the processor mode
and state indicated by the current value of the CPSR. The CPSR IT execution state bit is
restarted with the current value applying to the first instruction on restart.