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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-5
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8.2.2 Error checking and correction
The processor supports Error Checking and Correction (ECC) schemes for either 64-bits or
32-bits of data, and these have similar properties, although though the size of the data chunk that
the ECC scheme applies to is different. For each data chunk, either 32-bits or 64-bits, aligned,
a number of redundant code bits are computed and stored with the data. This enables the
processor to detect up to two errors in the data chunk or its code bits, and correct any single error
in the data chunk or its associated code bits. This is sometimes referred to as a
Single-Error-Correction, Double-Error-Detection (SEC-DED) ECC scheme.
If there are more than two errors in a data chunk and its associated code bits, they might or might
not be detected. The error scheme might interpret such a condition as a single-error and make
an unsuccessful attempt at a correction.
64-bit ECC
Eight code bits are computed for each 64 bits of data. The scheme can correct any single error
occurring in any doubleword, and detect any two errors occurring in any doubleword.
32-bit ECC
Seven code bits are computed for each 32 bits of data, so 14 bits of redundant data are required
for each doubleword. The scheme can correct two errors per doubleword, if they are in different
words. Four errors can be detected per doubleword, if there are two in each word.
8.2.3 Read-Modify-Write
The smallest unit of data that the processor can write is a byte. However, both the ECC schemes
are computed on data chucks that are larger than this. To write any data to a RAM protected with
ECC requires the error code for that data to be recomputed and rewritten. If the entire data chunk
is not written, for example, a halfword, 16-bits, is written to address
0x4
of a RAM with a 32-bit
error scheme, the error code must be computed partly from the data being written, and partly
from data already stored in the RAM. In this example, the halfword in the RAM at address
0x6
.
To compute the error code for such a write, the processor must first read data from the RAM,
then merge the data to be written with it, to compute the error code, then write the data to the
RAM, along with the new error code. This process is referred to as read-modify-write.
8.2.4 Hard errors
The errors described in this chapter are all assumed to be soft errors, that is, one or more bits of
the data stored in a RAM chunk are inverted. A new value can still be written to the RAM and
read back correctly, unless another soft error occurs in the meantime.
If the error in the memory is a hard error, that is, a physical failure of the RAM circuit so that a
bit can never be read or written reliably, the processor might not be able to correct and recover
from the error. The processor contains features that enable it to recover from some hard errors.
If you are implementing the processor and require these features, contact ARM to discuss the
features and your requirements.