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Programmer’s Model
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 2-8
ID013010 Non-Confidential, Unrestricted Access
For more information, see the ARM Architecture Reference Manual.
In Privileged modes, another register, the Saved Program Status Register (SPSR), is accessible.
This contains the condition code flags, status bits, and current mode bits saved as a result of the
exception that caused entry to the current mode.
Banked registers have a mode identifier that indicates which mode they relate to. Table 2-1lists
these identifiers.
FIQ mode has seven banked registers mapped to R8–R14 (R8_fiq–R14_fiq). As a result many
FIQ handlers do not have to save any registers.
The Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific
registers mapped to R13 and R14, permitting a private stack pointer and link register for each
mode.
Figure 2-3 on page 2-9 shows the register set, and those registers that are banked.
Table 2-1 Register mode identifiers
Mode Mode identifier
User
usr
a
a. The
usr
identifier is usually
omitted from register
names. It is only used in
descriptions where the User
or System mode register is
specifically accessed from
another operating mode.
Fast interrupt fiq
Interrupt irq
Supervisor svc
Abort abt
System
usr
a
Undefined und