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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-9
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Debug events
The debug logic in the processor can be configured to generate breakpoints or vector capture
events on instruction fetches, and watchpoints on data accesses. If the processor is
software-configured for monitor-mode debugging, an abort is taken when one of these events
occurs, or when a
BKPT
instruction is executed. For more details, see Chapter 11 Debug.
Precise and imprecise aborts
See Aborts on page 2-22 for more information about the differences between precise and
imprecise aborts.
8.3.2 Fault status information
When an abort occurs, information about the cause of the fault is recorded in a number of
registers, depending on the type of abort:
• Abort exceptions
• Precise abort exceptions on page 8-10
• Imprecise abort exceptions on page 8-10.
Abort exceptions
The following registers are updated when any abort exception is taken:
Link Register
The r14_abt register is updated to provide information about the address of the
instruction that the exception was taken on, in a similar way to other types of
exception. See Exceptions on page 2-16 for more details. This information can be
used to resume program execution after the abort has been handled.
Note
When a prefetch abort has occurred, ARM recommends that you do not use the
link register value for determining the aborting address, because 32-bit Thumb
instructions do not have to be word aligned and can cause an abort on either
halfword. This applies even if all of the code in the system does not use the extra
32-bit Thumb instructions introduced in ARMv6T2, because the earlier
BL
and
BLX
instructions are both 32 bits long. Use the Fault Address Register instead, as
described in this section.
Saved Program Status Register
The SPSR_abt register is updated to record the state and mode of the processor
when the exception was taken, in a similar way to other types of exception. See
Exceptions on page 2-16 for more details.
Fault Status Register
There are two fault status registers, one for prefetch aborts (IFSR) and one for
data aborts (DFSR). These record the type of abort that occurred, and whether it
occurred on a read or a write. In particular, this enables the abort handler to
distinguish between precise aborts, imprecise aborts, and debug events. For
details of the format of this register and the encodings used, see Fault Status and
Address Registers on page 4-45.