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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-71
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11.12 Debugging systems with energy management capabilities
The processor offers functionality for debugging systems with energy-management capabilities.
This section describes scenarios where the OS takes energy-saving measures when in an idle
state.
The different measures that the OS can take to save energy during an idle state are divided into
two groups:
Standby The OS takes measures that reduce energy consumption but maintain the
processor state.
Power down The OS takes measures that reduce energy consumption but do not maintain the
processor state. Recovery involves a reset of the processor after the power level
has been restored, and reinstallation of the processor state.
Standby is the least invasive OS energy-saving state because it only implies that the core is
unavailable. It does not clear any of the debug settings. For this case, the processor offers the
following:
• If the processor is in standby and a halting debug event occurs, the processor:
— leaves standby
— retires the Wait-For-Interrupt (
WFI
) instruction
— enters debug state.
• If the processor is in standby and detects an APB port access, it temporarily leaves standby
state to complete the transaction. While the processor wakes up from standby, the APB
access is held by keeping the PREADYDBG signal LOW.
11.12.1 Emulating power down
By writing to bit [0] of the PRCR, the debugger asserts the DBGNOPWRDWN output. The
expected usage model of this signal is that it connects to the system power controller and that,
when HIGH, it indicates that this controller must work in emulate mode.
On a power-down request from the processor, if the power controller is in emulate mode, it does
not remove processor power or ETM power. Otherwise, it behaves exactly the same as in normal
mode.
Emulating power down is ideal for debugging applications running on top of operating systems
that are free of errors because the debug register settings are not lost on a power-down event.
However, you must ensure that:
• nIRQ and nFIQ interrupts to the processor are externally masked as part of the emulation
to prevent them from retiring the
WFI
instruction from the pipeline.
• The reset controller asserts nRESET on power up, rather than nSYSPORESET.
Asserting nSYSPORESET on power up clears the debug registers inside the processor.
• The timing effects of power down and voltage stabilization are not factored in the
power-down emulation. This is the case for systems with voltage recovery controlled by
a closed loop system that monitors the processor supply voltage, rather than a fixed timed
for voltage recovery.
• The emulation does not model state lost during power down, making it possible to miss
errors in the state storage and recovery routines.