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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-16
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14.10 Processor state updating instructions
This section describes the cycle timing behavior for the
MSR
,
MRS
,
CPS
, and
SETEND
instructions.
Table 14-11 shows processor state updating instructions and their cycle timing behavior.
Table 14-11 Processor state updating instructions cycle timing behavior
Instruction Cycles Comments
MRS
1All
MRS
instructions
MSR
5 All other
MSR
instructions to the CPSR
MSR SPSR
1All
MSR
instructions to the SPSR
CPS <effect> <iflags>
1 Interrupt masks only
CPS <effect> <iflags>, #<mode>
1 Mode changing
SETEND
1-