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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-26
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4.2.11 Instruction Set Attributes Registers
There are eight Instruction Set Attributes Registers, ISAR0 to ISAR7, but three of these are
currently unused. This section describes:
• c0, Instruction Set Attributes Register 0, ISAR0
• c0, Instruction Set Attributes Register 1, ISAR1 on page 4-27
• c0, Instruction Set Attributes Register 2, ISAR2 on page 4-28
• c0, Instruction Set Attributes Register 3, ISAR3 on page 4-30
• c0, Instruction Set Attributes Register 4, ISAR4 on page 4-31
• c0, Instruction Set Attributes Registers 5-7 on page 4-32.
c0, Instruction Set Attributes Register 0, ISAR0
The Instruction Set Attributes Register 0 provides information about the instruction set that the
processor supports beyond the basic set.
The Instruction Set Attributes Register 0 is:
• a read-only register
• accessible in Privileged mode only.
Figure 4-19 shows the bit arrangement for Instruction Set Attributes Register 0.
Figure 4-19 Instruction Set Attributes Register 0 format
Table 4-14 shows how the bit values correspond with the Instruction Set Attributes Register 0
functions.
Reserved
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
Divide instructions
Debug instructions
Coprocessor instructions
Compare and branch instructions
Bitfield instructions
Bit count instructions
Atomic instructions
Table 4-14 Instruction Set Attributes Register 0 bit functions
Bits Field Function
[31:28] Reserved SBZ
[27:24] Divide instructions Indicates support for divide instructions.
0x1
, the processor supports
SDIV
and
UDIV
instructions.
[23:20] Debug instructions Indicates support for debug instructions.
0x1
, the processor supports
BKPT
.
[19:16] Coprocessor instructions Indicates support for coprocessor instructions other than separately attributed
feature registers, such as CP15 registers and VFP.
0x0
, no support.
[15:12] Compare and branch
instructions
Indicates support for combined compare and branch instructions.
0x1
, the processor supports combined compare and branch instructions,
CBNZ
and
CBZ
.