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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-23
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Errors on instruction cache read
All parity or ECC errors detected on instruction cache reads are correctable. If aborts are
enabled, a precise prefetch abort exception occurs. The instruction FAR gives the address that
caused the error to be detected. The instruction FSR indicates a parity error on a read. The
auxiliary FSR indicates that the error was in the cache and which cache Way the error was in.
Errors on data cache read
If parity or ECC aborts are enabled, or an uncorrectable ECC error is detected, a precise data
abort exception occurs. The data FAR gives the address that caused the error to be detected. The
data FSR indicates a precise read parity error. The auxiliary FSR indicates that the error was in
the cache and which cache Way the error was in.
Errors on data cache write
If parity or ECC aborts are enabled, or an uncorrectable ECC error is detected, an imprecise data
abort exception occurs. Because the abort is imprecise, the data FAR is Unpredictable. The data
FSR indicates an imprecise write parity error. The auxiliary FSR indicates that the error was in
the cache and which cache Way and Index the error was in.
In write-through cache regions the store that caused the error is written to external memory
using the L2 memory interface so data is not lost and the error is not fatal.
Errors on evictions
If the cache controller has determined a cache miss has occurred, it might have to do an eviction
before a linefill can take place. This can occur on reads, and on writes if write-allocation is
enabled for the region. Certain cache maintenance operations also generate evictions. If it is a
data-cache line which is dirty, an ECC error might be detected on the line being evicted:
• if the error is correctable, it is corrected inline before the data is written to the external
memory using the L2 memory interface
• if there is an uncorrectable error in the tag or dirty RAM, the write is not done and an
imprecise abort occurs
• if there is an uncorrectable error in the data RAM, the AXI master port WSTRBM signal
is deasserted for the word(s) with an error, and an imprecise abort occurs.
An imprecise abort can also occur on a correctable error depending on the Auxiliary Control
Register bits [5:3], see Auxiliary Control Registers on page 4-38. Any detected error is signaled
with the appropriate event.
Note
When parity checking is enabled, force write-though is always enabled. Therefore the cache
lines can never be dirty, and so evictions are not required. Force write-through can also be
enabled with ECC checking.
Errors on cache maintenance operations
The following sections describe errors on cache maintenance operations:
• Invalidate all instruction cache on page 8-24
• Invalidate all data cache on page 8-24
• Invalidate instruction cache by address on page 8-24
• Invalidate data cache by address on page 8-24