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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-14
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Table 9-15 shows possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM
for a Non-cacheable
LDR
or an
LDM
that transfers one register, an
LDM
1.
Table 9-16 show possible values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM
for a Non-cacheable
LDM
that transfers five registers (an
LDM
5).
0x4
(byte 4)
0x04
Incr 16-bit 1 data transfer
0x5
(byte 5)
0x04
Incr 32-bit 1 data transfer
0x6
(byte 6)
0x06
Incr 16-bit 1 data transfer
0x7
(byte 7)
0x07
Incr 32-bit 2 data transfers
Table 9-15 LDR or LDM1 from Non-cacheable Normal memory
Address[2:0] ARADDRM ARBURSTM ARSIZEM ARLENM
0x0
(byte 0) (word 0)
0x00
Incr 32-bit 1 data transfer
0x1
(byte 1)
0x01
Incr 64-bit 1 data transfer
0x2
(byte 2)
0x00
Incr 64-bit 1 data transfer
0x3
(byte 3)
0x00
Incr 64-bit 2 data transfers
0x4
(byte 4) (word 1)
0x04
Incr 32-bit 1 data transfer
0x5
(byte 5)
0x05
Incr 32-bit 2 data transfers
0x6
(byte 6)
0x06
Incr 16-bit 1 data transfer
0x08
Incr 16-bit 1 data transfer
0x7
(byte 7)
0x04
Incr 32-bit 2 data transfers
Table 9-16 LDM5, Non-cacheable Normal memory or cache disabled
Address[4:0] ARADDRM ARBURSTM ARSIZEM ARLENM
0x00
(word 0)
0x00
Incr 64-bit 3 data transfers
0x04
(word 1)
0x04
Incr 64-bit 3 data transfers
0x08
(word 2)
0x08
Incr 64-bit 3 data transfers
0x0C
(word 3)
0x0C
Incr 64-bit 3 data transfers
0x10
(word 4)
0x10
Incr 64-bit 2 data transfers
0x00
Incr 32-bit 1 data transfer
0x14
(word 5)
0x14
Incr 64-bit 2 data transfers
0x00
Incr 64-bit 1 data transfer
Table 9-14 LDRH from Non-cacheable Normal memory (continued)
Address[2:0] ARADDRM ARBURSTM ARSIZEM ARLENM