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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-10
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LDM that transfers five registers
Table 9-7 shows the values of ARADDRM, ARBURSTM, ARSIZEM, and ARLENM for a
Non-cacheable
LDM
that transfers five registers (an
LDM
5) in Strongly Ordered or Device memory.
Note
A load-multiple from address
0x1
,
0x2
,
0x3
,
0x5
,
0x6
,
0x7
,
0x9
,
0xA
,
0xB
,
0xD
,
0xE
, or
0xF
generates
an alignment fault.
Table 9-7 LDM5, Strongly Ordered or Device memory
Address[4:0] ARADDRM ARBURSTM ARSIZEM ARLENM
0x00
(word 0)
0x00
Incr 32-bit 5 data transfers
0x04
(word 1)
0x04
Incr 32-bit 5 data transfers
0x08
(word 2)
0x08
Incr 32-bit 5 data transfers
0x0C
(word 3)
0x0C
Incr 32-bit 5 data transfers