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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-26
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14.16 Coprocessor instructions
This section describes the cycle timing behavior for the
MCR
and
MRC
instructions to CP14, the
debug coprocessor or CP15, the system control coprocessor.
The precise timing of coprocessor instructions is tightly linked with the behavior of the relevant
coprocessor. Table 14-21 shows the coprocessor instructions cycle timing behavior. Table 14-21
shows the best case numbers.
Note
Some instructions such as cache operations take more cycles.
Table 14-21 Coprocessor instructions cycle timing behavior
Instruction Cycles Result latency Comments
MCR
6- -
MCR <cond>
6 - Condition code passes
4 - Condition code fails
MRC
66 -
MRC <cond>
6 6 Condition code passes
4 4 Condition code fails