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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xiv
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Figure 4-16 Memory Model Feature Register 1 format ................................................................................ 4-23
Figure 4-17 Memory Model Feature Register 2 format ................................................................................ 4-24
Figure 4-18 Memory Model Feature Register 3 format ................................................................................ 4-25
Figure 4-19 Instruction Set Attributes Register 0 format .............................................................................. 4-26
Figure 4-20 Instruction Set Attributes Register 1 format .............................................................................. 4-27
Figure 4-21 Instruction Set Attributes Register 2 format .............................................................................. 4-29
Figure 4-22 Instruction Set Attributes Register 3 format .............................................................................. 4-30
Figure 4-23 Instruction Set Attributes Register 4 format .............................................................................. 4-31
Figure 4-24 Current Cache Size Identification Register format .................................................................... 4-33
Figure 4-25 Current Cache Level ID Register format ................................................................................... 4-34
Figure 4-26 Cache Size Selection Register format ...................................................................................... 4-35
Figure 4-27 System Control Register format ................................................................................................ 4-36
Figure 4-28 Auxiliary Control Register format .............................................................................................. 4-38
Figure 4-29 Secondary Auxiliary Control Register format ............................................................................ 4-42
Figure 4-30 Coprocessor Access Register format ....................................................................................... 4-44
Figure 4-31 Data Fault Status Register format ............................................................................................. 4-46
Figure 4-32 Instruction Fault Status Register format .................................................................................... 4-47
Figure 4-33 Auxiliary fault status registers format ........................................................................................ 4-48
Figure 4-34 MPU Region Base Address Registers format ........................................................................... 4-50
Figure 4-35 MPU Region Size and Enable Registers format ....................................................................... 4-51
Figure 4-36 MPU Region Access Control Register format ........................................................................... 4-52
Figure 4-37 MPU Memory Region Number Register format ........................................................................ 4-53
Figure 4-38 Cache operations ...................................................................................................................... 4-55
Figure 4-39 c7 format for Set and Way ........................................................................................................ 4-56
Figure 4-40 Cache operations address format ............................................................................................. 4-56
Figure 4-41 BTCM Region Registers ........................................................................................................... 4-58
Figure 4-42 ATCM Region Registers ........................................................................................................... 4-59
Figure 4-43 Slave Port Control Register ...................................................................................................... 4-60
Figure 4-44 nVAL IRQ Enable Set Register format ...................................................................................... 4-62
Figure 4-45 nVAL FIQ Enable Set Register format ...................................................................................... 4-63
Figure 4-46 nVAL Reset Enable Set Register format ................................................................................... 4-64
Figure 4-47 nVAL Debug Request Enable Set Register format ................................................................... 4-6
5
Figure 4-48 nVAL IRQ Enable Clear Register format .................................................................................. 4-66
Figure 4-49 nVAL FIQ Enable Clear Register format ................................................................................... 4-66
Figure 4-50 nVAL Reset Enable Clear Register format ............................................................................... 4-67
Figure 4-51 nVAL Debug Request Enable Clear Register format ................................................................ 4-68
Figure 4-52 nVAL Cache Size Override Register format ............................................................................. 4-69
Figure 4-53 Correctable Fault Location Register - cache ............................................................................. 4-70
Figure 4-54 Correctable Fault Location Register - TCM .............................................................................. 4-71
Figure 4-55 Build Options 1 Register format ................................................................................................ 4-72
Figure 4-56 Build Options 2 Register format ................................................................................................ 4-73
Figure 6-1 PMNC Register format ................................................................................................................ 6-7
Figure 6-2 CNTENS Register format ............................................................................................................ 6-9
Figure 6-3 CNTENC Register format ......................................................................................................... 6-10
Figure 6-4 FLAG Register format ............................................................................................................... 6-11
Figure 6-5 SWINCR Register format .......................................................................................................... 6-12
Figure 6-6 PMNXSEL Register format ....................................................................................................... 6-12
Figure 6-7 EVTSELx Register format ......................................................................................................... 6-14
Figure 6-8 USEREN Register format ......................................................................................................... 6-15
Figure 6-9 INTENS Register format ........................................................................................................... 6-16
Figure 6-10 INTENC Register format ........................................................................................................... 6-17
Figure 7-1 Overlapping memory regions ...................................................................................................... 7-5
Figure 7-2 Overlay for stack protection ........................................................................................................ 7-5
Figure 7-3 Overlapping subregion of memory .............................................................................................. 7-6
Figure 8-1 L1 memory system block diagram .............................................................................................. 8-3
Figure 8-2 Error detection and correction schemes ..................................................................................... 8-4
Figure 8-3 Nonsequential read operation performed with one RAM access. ............................................. 8-28
Figure 8-4 Sequential read operation performed with one RAM access .................................................... 8-28
Figure 11-1 Typical debug system ............................................................................................................... 11-2
Figure 11-2 Debug ID Register format ....................................................................................................... 11-11