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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-29
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Data RAM sizes without parity or ECC implemented
Table 8-9 shows the organization for instruction and data caches when neither parity nor ECC
is implemented.
Data RAM sizes with parity implemented
Table 8-11 shows the organization for instruction and data caches when parity is implemented.
For parity error detection, one bit is added per byte, so four bits are added for each RAM bank.
Table 8-9 Instruction cache data RAM sizes, no parity or ECC
Cache size Data RAMs
4KB, 4 1KB ways 4 banks 64 bits 128 lines or
8 banks 32 bits 128 lines
8KB, 4 2KB ways 4 banks 64 bits 256 lines or
8 banks 32 bits 256 lines
16KB, 4 4KB ways 4 banks 64 bits 512 lines or
8 banks 32 bits 512 lines
32KB, 4 8KB ways 4 banks 64 bits 1024 lines or
8 banks 32 bits 1024 lines
64KB, 4 16KB ways 4 banks 64 bits 2048 lines or
8 banks 32 bits 2048 lines
Table 8-10 Data cache data RAM sizes, no parity or ECC
Cache size Data RAMs
4KB, 4 1KB ways 8 banks 32 bits 128 lines
8KB, 4 2KB ways 8 banks 32 bits 256 lines
16KB, 4 4KB ways 8 banks 32 bits 512 lines
32KB, 4 8KB ways 8 banks 32 bits 1024 lines
64KB, 4 16KB ways 8 banks 32 bits 2048 lines
Table 8-11 Instruction cache data RAM sizes, with parity
Cache size Data RAMs
4KB, 4 1KB ways 4 banks 72 bits 128 lines or
8 banks 36 bits 128 lines
8KB, 4 2KB ways 4 banks 72 bits 256 lines or
8 banks 36 bits 256 lines
16KB, 4 4KB ways 4 banks 72 bits 512 lines or
8 banks 36 bits 512 lines
32KB, 4 8KB ways 4 banks 72 bits 1024 lines or
8 banks 36 bits 1024 lines
64KB, 4 16KB ways 4 banks 72 bits 2048 lines or
8 banks 36 bits 2048 lines