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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-16
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When either the LSU or the AXI slave interface is performing a read-modify-write operation on
a TCM port, various internal data hazards exist for either the AXI-slave interface or the LSU.
In these cases, additional stall cycles are generated, beyond those normally required for
arbitration. For optimum performance of the processor when configured with ECC, ensure that
all write bursts to the TCM from the AXI slave interface write an entire data chunk, that is,
32-bits or 64-bits, naturally aligned, depending on the error scheme.
8.4.5 TCM initialization
You can enable the processor to boot from the ATCM or the BTCM. The INITRAMA and
INITRAMB pins, when tied HIGH, enable the ATCM and the BTCM respectively on leaving
reset. The LOCZRAMA pin forces one of the TCMs to have its base address at
0x0
. If
LOCZRAMA is tied HIGH, the initial base address of the ATCM is
0x0
, otherwise the initial
base address of the BTCM is
0x0
. In both cases, the initial base address of the other TCM is
implementation-defined, see Configurable options on page 1-13.
The ATCM Region Register and BTCM Region Register respectively determine the base
address for the ATCM and BTCM. For information on how to read the TCM region registers,
see c9, BTCM Region Register on page 4-57 or c9, ATCM Region Register on page 4-58 as
appropriate. For information about pre-loading data into the TCMs, see TCM on page 3-3.
8.4.6 TCM port protocol
Each TCM port operates independently to read and write data to and from the memory attached
to it. Information about which memory location is to be accessed is passed on the TCM port
along with write data and associated error code or parity bits, if appropriate. In addition, the
TCM port provides information about whether the access results from an instruction fetch from
the PFU, a data access from the LSU, or a DMA transfer from the AXI slave interface. Each
TCM port also has an associated parity bit, computed from the address and control signals for
that port.
Read data and associated error code or parity bits are read back from the TCM port. In addition,
the TCM memory controller can indicate that the processor must wait one or more cycles before
reading the response, or signal that an error has occurred and must be either aborted or retried.
For more information about TCM errors, see External TCM errors.
For more information about TCM port protocol, the signals and timing, see the Cortex-R4 and
Cortex-R4F Integration Manual.
8.4.7 External TCM errors
Each TCM port has a number of features that support the integration of a TCM RAM with an
error checking scheme implemented in the RAM controller logic outside of the processor, that
is, by the integrator.
Errors can be signaled to each TCM port if the external error checking scheme detects one and,
if enabled, the processor generates an instruction or data abort or an AXI error response as
appropriate. On a TCM read from either the instruction-side or data-side, the TCM controller
can indicate that the read must be retried instead of generating an abort.
You can enable external errors for each TCM port individually by setting the appropriate bits in
the Auxiliary Control Register. See c1, Auxiliary Control Register on page 4-38. If external
errors are not enabled for a TCM port, the processor ignores any error signaled on that port. You
can pin-configure the processor to set the enable bits, and therefore enable external error
checking on reset, by tying off the ERRENRAM input as required.