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Processor Initialization, Resets, and Clocking
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 3-5
ID013010 Non-Confidential, Unrestricted Access
• Turn on 64-bit store behavior using CP15. See c15, Secondary Auxiliary Control Register
on page 4-41.
• Write to the TCM using any store instructions, or any AXI write transactions. The
processor performs read-modify-write accesses to ensure that all writes are to 64-bit
aligned quantities, even though error checking is turned off.
Note
You can enable error checking and 64-bit store behavior on a per-TCM interface basis.
References above to these controls relate to whichever TCM is being initialized.
Using TCMs from reset
The processor can be pin-configured to enable the TCM interfaces from reset, and to select the
address at which each TCM appears from reset. See TCM initialization on page 8-16 for more
details. This enables you to configure the processor to boot from TCM but, to do this, the TCM
must first be preloaded with the boot code. The nCPUHALT pin can be asserted while the
processor is in reset to stop the processor from fetching and executing instructions after coming
out of reset. While the processor is halted in this way, the TCMs can be preloaded with the
appropriate data. When the nCPUHALT pin is deasserted, the processor starts fetching
instructions from the reset vector address in the normal way.
Note
When it has been deasserted to start the processor fetching, nCPUHALT must not be asserted
again except when the processor is under processor or power-on reset, that is, nRESET
asserted. The processor does not halt if the nCPUHALT pin is asserted while the processor is
running.