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Level Two Interface
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 9-2
ID013010 Non-Confidential, Unrestricted Access
9.1 About the L2 interface
This section describes the processor L2 interface. The L2 interface consists of AXI master and
AXI slave interfaces.
The processor is designed for use in larger chip designs using the Advanced Microcontroller Bus
Architecture (AMBA) AXI protocol. The processor uses the L2 interfaces as its interface to
memory and peripheral devices.
External AXI masters and the processor can use the AXI slave interface to access the processor
RAMs. You can use the AXI slave interface for DMA access into and out of the TCMs or to
perform software test of the TCMs and cache RAMs.