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Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-34
ID013010 Non-Confidential, Unrestricted Access
8.6 Internal exclusive monitor
The processor L1 memory system has an internal exclusive monitor. This is a two state, open
and exclusive, state machine that manages load/store exclusive (
LDREXB
,
LDREXH
,
LDREX
,
LDREXD
,
STREXB
,
STREXH
,
STREX
and
STREXD
) accesses and clear exclusive (
CLREX
) instructions. You can use
these instructions, operating in the L1 memory system, to construct semaphores and ensure
synchronization between different processes. By adding an external exclusive monitor, you can
also use these instructions in the L2 memory system to construct semaphores and ensure
synchronization between different processors. See the ARM Architecture Reference Manual for
more information about how these instructions work.
When a load-exclusive access is performed, the internal exclusive monitor moves to the
exclusive state. It moves back to the open state when a store exclusive access or clear exclusive
instruction is performed. The internal exclusive monitor holds exclusivity state for the
Cortex-R4 processor only. It does not record the address of the memory that a load-exclusive
access was performed to. Any store exclusive access performed when the state is open fails. If
the state is exclusive, the access passes if it is to non-shared memory but, if it is to shared
memory, the access must be performed as an exclusive using the L2 memory interface. Whether
the shared store-exclusive access passes or fails depends on the state of an external exclusive
monitor which can track accesses made by other processors in the system.