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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-33
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11.5.2 Claim Registers
The Claim Tag Set Register and the Claim Tag Clear Register enable an external debugger to
claim debug resources.
Claim Tag Set Register
Figure 11-16 shows the bit arrangement of the Claim Tag Set Register.
Figure 11-16 Claim Tag Set Register format
Table 11-27 shows how the bit values correspond with the Claim Tag Set Register functions.
0xD10
836 MPUIR MPU Type Register
0xD14
837 MPIDR Multiprocessor Affinity Register
0xD18-0xD1C
838-839 - Alias of MIDR
0xD20
840 ID_PFR0 Processor Feature Register 0
0xD24
841 ID_PFR1 Processor Feature Register 1
0xD28
842 ID_DFR0 Debug Feature Register 0
0xD2C
843 ID_AFR0 Auxiliary Feature Register 0
0xD30
844 ID_MMFR0 Processor Feature Register 0
0xD34
845 ID_MMFR1 Processor Feature Register 1
0xD38
846 ID_MMFR2 Processor Feature Register 2
0xD3C
847 ID_MMFR3 Processor Feature Register 3
0xD40
848 ID_ISAR0 ISA Feature Register 0
0xD44
849 ID_ISAR1 ISA Feature Register 1
0xD48
850 ID_ISAR2 ISA Feature Register 2
0xD4C
851 ID_ISAR3 ISA Feature Register 3
0xD50
852 ID_ISAR4 ISA Feature Register 4
0xD54
853 ID_ISAR5 ISA Feature Register 5
Table 11-26 Processor Identifier Registers (continued)
Offset (hex) Register number Mnemonic Function
31 0
Reserved
78
Claim tag set
Table 11-27 Claim Tag Set Register functions
Bits Field Function
[31:8] Reserved RAZ or SBZP.
[7:0] Claim tag set RAO. Sets claim tags on writes.