ARM r1p3 Computer Hardware User Manual


 
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-1
ID013010 Non-Confidential, Unrestricted Access
Chapter 14
Cycle Timings and Interlock Behavior
This chapter describes the cycle timings and interlock behavior of instructions on the processor. It
contains the following sections:
About cycle timings and interlock behavior on page 14-3
Register interlock examples on page 14-6
Data processing instructions on page 14-7
QADD, QDADD, QSUB, and QDSUB instructions on page 14-9
Media data-processing on page 14-10
Sum of Absolute Differences (SAD) on page 14-11
Multiplies on page 14-12
Divide on page 14-14
Branches on page 14-15
Processor state updating instructions on page 14-16
Single load and store instructions on page 14-17
Load and Store Double instructions on page 14-20
Load and Store Multiple instructions on page 14-21
RFE and SRS instructions on page 14-24
Synchronization instructions on page 14-25
Coprocessor instructions on page 14-26
SVC, BKPT, Undefined, and Prefetch Aborted instructions on page 14-27
Miscellaneous instructions on page 14-28
Floating-point register transfer instructions on page 14-29
Floating-point load/store instructions on page 14-30
Floating-point single-precision data processing instructions on page 14-32