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FPU Programmer’s Model
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 12-11
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12.5 Compliance with the IEEE 754 standard
When Default NaN (DN) and Flush-to-Zero (FZ) modes are disabled, the VFP functionality is
compliant with the IEEE 754 standard in hardware. No support code is required to achieve this
compliance.
See the ARM Architecture Reference Manual for information about VFP architecture
compliance with the IEEE 754 standard.
12.5.1 Complete implementation of the IEEE 754 standard
The following operations from the IEEE 754 standard are not supplied by the VFP instruction
set:
• remainder
• round floating-point number to integer-valued floating-point number
• binary-to-decimal conversions
• decimal-to-binary conversions
• direct comparison of single-precision and double-precision values.
For complete implementation of the IEEE 754 standard, VFP functionality must be augmented
with library functions that implement these operations. See Application Note 98, VFP Support
Code for information on the available library functions.
12.5.2 IEEE 754 standard implementation choices
Some of the implementation choices permitted by the IEEE 754 standard and used in the VFPv3
architecture are described in the ARM Architecture Reference Manual.
NaN handling
All single-precision and double-precision values with the maximum exponent field value and a
nonzero fraction field are valid NaNs. A most significant fraction bit of zero indicates a
Signaling NaN (SNaN). A one indicates a Quiet NaN (QNaN). Two NaN values are treated as
different NaNs if they differ in any bit. Table 12-8 shows the default NaN values in both
single-precision and double-precision.
Processing of input NaNs for ARM floating-point functionality and libraries is defined as
follows:
• In full-compliance mode, NaNs are handled as described in the ARM Architecture
Reference Manual. The hardware processes the NaNs directly for arithmetic
CDP
instructions. For data transfer operations, NaNs are transferred without raising the Invalid
Operation exception. For the non-arithmetic
CDP
instructions,
VABS
,
VNEG
, and
VMOV
, NaNs
are copied, with a change of sign if specified in the instructions, without causing the
Invalid Operation exception.
Table 12-8 Default NaN values
Single-precision Double-precision
Sign 0 0
Exponent
0xFF 0x7FF
Fraction bit [22] = 1, bits [21:0] are all zeros bit [51] = 1, bits [50:0] are all zeros