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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-74
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[25:24] BTCM_ES Indicates whether an error scheme is implemented on the BTCM interface(s):
00 = no error scheme
01 = 8-bit parity logic
10 = 32-bit error detection and correction
11 = 64-bit error detection and correction.
[23] NO_IE Indicates whether the processor supports big-endian instructions:
0 = processor supports big-endian instructions
1 = processor does not support big-endian instructions.
[22] NO_FPU Indicates whether the processor contains a floating point unit:
0 = processor contains a floating point unit
1 = processor does not contain a floating point unit.
[21] NO_MPU Indicates whether the processor contains a Memory Protection Unit (MPU):
0 = processor contains an MPU
1 = processor does not contain an MPU.
[20] MPU_REGIONS Indicates the number of regions in the included MPU:
0 = 8
1 = 12.
If the processor does not contain an MPU (bit [21] set to 0), this bit is set to 0.
[19:17] BREAK_POINTS Indicates the number of break points implemented in the processor, minus 1.
[16:14] WATCH_POINTS Indicates the number of watch points implemented in the processor, minus 1.
[13] NO_A_TCM_INF Indicates whether the processor contains an ATCM port:
0 = processor contains ATCM port
1 = processor does not contain ATCM port.
[12] NO_B0_TCM_INF Indicates whether the processor contains a B0TCM port:
0 = processor contains B0TCM port
1 = processor does not contain B0TCM port.
[11] NO_B1_TCM_INF Indicates whether the processor contains a B1TCM port:
0 = processor contains B1TCM port
1 = processor does not contain B1TCM port.
[10] TCMBUSPARITY Indicates whether the processor contains TCM address bus parity logic:
0 = processor does not contain TCM address bus parity logic
1 = processor contains TCM address bus parity logic.
[9] NO_SLAVE Indicates whether the processor contains an AXI slave port:
0 = processor contains an AXI slave port
1 = processor does not contain an AXI slave port.
[8:7] ICACHE_ES Indicates whether an error scheme is implemented for the instruction cache:
00 = no error scheme
01 = 8-bit parity error detection
11 = 64-bit error detection and correction.
If the processor does not contain an i-cache, these bits are set to 00.
Table 4-55 Build Options 2 Register (continued)
Bits Field Function