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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-14
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4.2.2 c0, Main ID Register
The Main ID Register returns the device ID code that contains information about the processor.
The Main ID Register is:
• a read-only register
• accessible in Privileged mode only.
Figure 4-7 shows the arrangement of bits in the register.
Figure 4-7 Main ID Register format
1 Build Options 2 Read-only
-
d
page 4-72
2-7 Undefined - - -
c3 0 Correctable Fault Location Read/write Unpredictable page 4-70
1-7 Undefined - - -
c4 0-7
c5 0 Invalidate all data cache Write-only - page 4-55
1-7 Undefined - - -
c6-c13 0-7
c15 0 c14 0 Cache Size Override Write-only - page 4-69
1-7 Undefined - - -
c15 0-7
a. The value of bits [23:20,3:0] of the Main ID Register depend on product revision. See the register description for more
information.
b. Reset value depends on number of MPU regions.
c. Reset value depends on the cache size implemented.
d. See register description for more information.
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page
VariantImplementor
31 23 20 19 16 15 4 3 0
Architecture Primary part number Revision
24