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Memory Protection Unit
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 7-10
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7.3.1 Cacheable memory policies
When TEX[2] == 1, the memory region is Cacheable memory, and the rest of the encoding
defines the Inner and Outer cache policies:
TEX[1:0] defines the Outer cache policy
C,B defines the Inner cache policy
The same encoding is used for the Outer and Inner cache policies. Table 7-4 shows the
encoding.
When the processor performs a memory access through its AXI bus master interface:
• the Inner attributes are indicated on the A*USERM signals. For the encodings, see
Table 9-3 on page 9-5
• the Outer attributes are indicated on the and A*CACHEM signals. For the encodings, see
Table 9-2 on page 9-5.
For more information on region attributes, see the ARM Architecture Reference Manual.
010 1 X Reserved. - -
011 X X Reserved. - -
1BB A A Cacheable memory:
AA
b
= Inner policy
BB
b
= Outer policy
Normal
S bit
a
a. Region is Shareable if S == 1, and Non-shareable if S == 0.
b. Table 7-4 shows the encoding for these bits.
Table 7-3 TEX[2:0], C, and B encodings (continued)
TEX[2:0] C B Description Memory Type Shareable?
Table 7-4 Inner and Outer cache policy encoding
Memory attribute encoding Cache policy
00 Non-cacheable
01 Write-back, write-allocate
10 Write-through, no write-allocate
11 Write-back, no write-allocate