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System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-67
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Table 4-47 shows how the bit values correspond with the FIQ Enable Clear Register.
To access the FIQ Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 5 ; Read FIQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 5 ; Write FIQ Enable Clear Register
On reads, this register returns the current setting. On writes, overflow interrupt requests that are
currently enabled can be disabled.
For information on how to enable FIQ requests on counter overflows, and how the requests are
signaled, see c15, nVAL FIQ Enable Set Register on page 4-63.
c15, nVAL Reset Enable Clear Register
The nVAL Reset Enable Clear Register disables overflow reset requests from any of the PMC
Registers, PMC0-PMC2, and CCNT, that are enabled.
The nVAL Reset Enable Clear Register is:
• A read/write register.
• Always accessible in Privileged mode. The USEREN Register determines access, see c9,
User Enable Register on page 6-15.
Figure 4-50 shows the bit arrangement for the nVAL Reset Enable Clear Register.
Figure 4-50 nVAL Reset Enable Clear Register format
Table 4-48 shows how the bit values correspond with the nVAL Reset Enable Clear Register.
Table 4-47 nVAL FIQ Enable Clear Register bit functions
Bits Field Function
[31] C CCNT overflow FIQ request
[30:3] Reserved UNP or SBZP
[2] P2 PMC2 overflow FIQ request
[1] P1 PMC1 overflow FIQ request
[0] P0 PMC0 overflow FIQ request
C
31 3210
Reserved
P2
P1
P0
Performance monitor counter overflow
reset request disables
Cycle count overflow
reset request disable
Table 4-48 nVAL Reset Enable Clear Register bit functions
Bits Field Function
[31] C CCNT overflow reset request
[30:3] Reserved UNP or SBZP