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ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 11-9
ID013010 Non-Confidential, Unrestricted Access
OS Lock The processor does not support OS Lock.
Note
• These locks are set to their reset values only on reset of the debug logic, provided by
PRESETDBGn.
• You must set the PADDRDBG31 input signal to 1 for accesses originated from the
external debugger for the Software Lock override feature to work.
Table 11-4 External debug interface access permissions
Registers
PADDRDBG31 Lock DRCR, PRCR, PRSR Other Debug registers LAR Other registers
X
X
a
NPOSS
b
NPOSS
b
NPOSS
b
NPOSS
b
1
X
a
OK
c
OK
c
OK
c
OK
c
0
1
d
WI
e
WI
e
OK
c
WI
e
00
OK
c
OK
c
OK
c
OK
c
a. X indicates that the outcome does not depend on this condition.
b. Not possible. Accessing debug registers while the processor is powered down is not possible.
c. OK indicates that the access succeeds.
d. LSR[1] bit is set.
e. WI indicates that writes are ignored.