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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-31
ID013010 Non-Confidential, Unrestricted Access
First address not 64-bit aligned
VLDM{mode}.32 <Rn>{!}, {s1}
11 11 -
VLDM{mode}.32 <Rn>{!}, {s1,s2}
2 2 1,2 2 -
VLDM{mode}.32 <Rn>{!}, {s1-s3}
2 3 1,2,2 3 -
VLDM{mode}.32 <Rn>{!}, {s1-s4}
3 3 1,2,2,3 3 -
VLDM{mode}.64 <Rn>{!}, {d1}
22 22 -
VLDM{mode}.64 <Rn>{!}, {d1,d2}
3 3 2,3 3 -
VLDM{mode}.64 <Rn>{!}, {d1-d3}
4 4 2,3,4 4 -
VLDM{mode}.64 <Rn>{!}, {d1-d4}
5 5 2,3,4,5 5 -
Table 14-25 Floating-point load/store instructions cycle timing behavior (continued)
Example instruction
Cycles/
memory
cycles
Cycles with
writeback (!)
Result
latency
(load)
Result
latency
(base
register,
<Rn>)
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