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Introduction
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 1-12
ID013010 Non-Confidential, Unrestricted Access
1.5 Power management
The processor includes several microarchitectural features to reduce energy consumption:
• Accurate branch and return prediction, reducing the number of incorrect instruction fetch
and decode operations.
• The caches use sequential access information to reduce the number of accesses to the tag
RAMs and to unmatched data RAMs.
• Extensive use of gated clocks and gates to disable inputs to unused functional blocks.
Because of this, only the logic actively in use to perform a calculation consumes any
dynamic power.
The processor uses four levels of power management:
Run mode This mode is the normal mode of operation where all of the functionality
of the processor is available.
Standby mode This mode disables most of the clocks of the device, while keeping the
device powered up. This reduces the power drawn to the static leakage
current and the minimal clock power overhead required to enable the
device to wake up from the Standby mode.
Shutdown mode This mode has the entire device powered down. All state, including cache
and TCM state, must be saved externally. The assertion of reset returns the
processor to the run state.
Dormant mode The processor can be implemented in such a way as to support Dormant
mode. Dormant mode is a power saving mode in which the processor
logic, but not the processor TCM and cache RAMs, is powered down. The
processor state, apart from the cache and TCM state, is stored to memory
before entry into Dormant mode, and restored after exit.
For more information on preparing the Cortex-R4 to support Dormant
mode, contact ARM.
For more information on the power management features, see Chapter 10 Power Control.