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Theory of Operation (2635A)
Detailed Circuit Description
2A
2A-35
The second four-bit counter is controlled by an open-drain output on the Display
Controller (A2U1-17) and pull-down resistor A2R1. When the beeper (A2LS1) is off,
A2U1-17 is pulled to ground by A2R1. This signal is then inverted by A2U6, with
A2U6-6 driving the CLR input high to hold the four-bit counter reset. Output A2U4-8 of
the four-bit counter drives the parallel combination of the beeper (A2LS1) and A2R10 to
ground to keep the beeper silent. When commanded by the Microprocessor, the Display
Controller drives A2U1-17 high, enabling the beeper and driving the CLR input of the
four-bit counter (A2U4-12) low. A 4-kHz square wave then appears at counter output
A2U4-8 and across the parallel combination of A2LS1 and A2R10, causing the beeper to
resonate.
2A-68. Watchdog Timer and Reset Circuit
The Watchdog Timer and Reset circuit has been defeated by the insertion of the jumper
between TP1 and TP3 on the Display Assembly. In this instrument, the reset circuitry is
on the Main Assembly and the Watchdog Timer is part of the Microprocessor (A1U1).
The Display Reset signal (DRST*) drives the RESET2* signal on the Display Assembly
low when the instrument is being reset. This discharges capacitor A2C3, and NAND gate
output A2U6-11 provides an active high reset signal to the Display Processor. The
Watchdog Timer on the Display Assembly (A2U5, A2U6 and various resistive and
capacitive timing components) is held "cleared" by TP1 being held at 0V dc by a jumper,
and output A2U5-12 will always be high.
2A-69. Display Controller
The Display Controller is a four-bit, single-chip microcomputer with high-voltage
outputs that are capable of driving a vacuum-fluorescent display directly. The controller
receives commands over a three-wire communication channel from the Microprocessor
on the Main Assembly. Each command is transferred serially to the Display Controller
on the display transmit (DISTX) signal, with bits being clocked into the Display
Controller on the rising edges of the display clock signal (DSCLK). Responses from the
Display Controller are sent to the Microprocessor on the display receive signal (DISRX)
and are clocked out of the Display Controller on the falling edge of DSCLK.
Series resistor A2R11 isolates DSCLK from A2U1-40, preventing this output from
trying to drive A1U1-77 directly. Figure 2A-8 shows the waveforms during a single
command byte transfer. Note that a high DISRX signal is used to hold off further
transfers until the Display Controller has processed the previously received byte of the
command.
BIT 7
BIT 7
HOLD OFF
CLEAR TO
RECEIVE
31.5 µs
DISTX
DSCLK
DISRX
CLEAR TO
RECEIVE
31.5 µs
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
s18f.eps
Figure 2A-8. Command Byte Transfer Waveforms (2635A)