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Service Manual
7-4
7-5. Main PCA Connector
The IEEE-488 PCA interfaces to the Main PCA through a 26-pin, right-angle connector
(A5J1). This connector routes the 8-bit data bus, the lower three bits of the address bus,
memory control, system clock, and address decode signals from the Main PCA to the
IEEE-488 PCA. The IRQ2* interrupt request signal is routed from the IEEE-488 PCA to
the Main PCA. The IEEE-488 PCA is powered by the +5.1V dc power supply (VCC).
The IEEE-488 PCA is sensed by the Microprocessor on the Main PCA through the
connection of logic common to the option sense signal OPS* (A5J1-22).
7-6. IEEE-488 Controller
The IEEE-488 Controller (A5U1) is an integrated circuit that performs the transfer of
information between the IEEE-488 standard bus and the Main PCA Microprocessor
(A1U4). Once it has been programmed by the Microprocessor via the eight-register
microprocessor interface, A5U1 performs IEEE-488 bus transactions independently until
it must interrupt the Microprocessor for additional information or data.
The IEEE-488 Controller is clocked by a 1.2288-MHz square-wave clock. This clock
(A5U1-20) is generated by the Microprocessor. The IEEE-488 Controller uses this clock
to run the internal state machines that handle IEEE-488 bus transactions. The IEEE-488
Controller is reset when the system RESET* signal (A5U1-21) is low.
For each character that it receives or transmits, the IEEE-488 Controller generates an
interrupt to the Microprocessor. These interrupts are generated by driving the open-drain
interrupt output A5U1-10 low. This signal drives the IRQ2* input to the Microprocessor
low. When the Microprocessor responds to the interrupt and takes the necessary actions
by reading and writing registers in the IEEE-488 Controller, A5U1-10 goes high again.
Resistor A5R1 provides a pull-up termination on open-drain interrupt output A5U1-10.
When the Microprocessor performs a memory cycle to the IEEE-488 Controller, the
lower three bits of the address bus select the register being accessed in A5U1. When a
memory read cycle is performed, chip-enable A5U1-4 goes low, and A5U1-6 (DBIN)
goes high. These actions enable A5U1, driving the contents of the selected register onto
the data bus to the Microprocessor. When a memory write cycle is performed, chip-
enable A5U1-4 goes low, and A5U1-5 (WE*) goes first low and then high to latch the
data being driven from the Microprocessor into the IEEE-488 Controller.
The IEEE-488 Controller interfaces to the IEEE-488 Transceivers using an eight-bit data
bus, eight interface signals, and two transceiver control signals (A5U1-33 and A5U1-
23).
The controller-in-charge signal (A5U1-33), which should always be high, controls the
direction of the SRQ, ATN, IFC, and REN IEEE-488 transceivers in A5U3.
The talk enable output (A5U1-2) is either low when the IEEE-488 Controller is not
addressed to talk or high when the controller is addressed to talk. This signal determines
the direction of all IEEE-488 Transceivers except SRQ, ATN, IFC, and REN.