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Diagnostic Testing and Troubleshooting (2635A)
Totalizer Troubleshooting
5A
5A-23
If the Input Buffer does not function correctly, the problem is probably A1Z1, A1Z3, or
the associated comparator (A1U3 or A1U4). If the Input Buffer functions correctly, but
Hydra is not able to read the state of the Digital Input correctly, the problem is most
likely the FPGA (A1U25). If Hydra is not able to read the states of any of the eight
Digital Inputs correctly, the problem is most likely in the address signals going to the
FPGA (A1U25-85, A1U25-90, A1U25-96, A1U25-97).
5A-17. Totalizer Troubleshooting
Power up Hydra while holding down the CANCL button to reset the instrument
configuration. Verify that the Input Buffer Threshold circuit generates approximately
1.4V dc at A1TP18. Drive the Totalizer Input (A1J5-2) with a signal generator
outputting a 100-Hz square wave that transitions from 0 to +5V dc. The signal generator
output common should be connected to Common (A1J5-1). Verify that the output of the
Input Buffer (A1U8-1) is a 100-Hz square wave that is the inverse of the input signal.
Verify also that the input to the totalizer counter (A1TP20) is a buffered form of the
signal just verified at the output of the Input Buffer.
Use the following procedure to troubleshoot the totalizer input debouncer, Enable the
totalizer debouncer by sending the TOTAL_DBNC 1 Computer Interface command to
the instrument. With the signal generator still connected and outputting a 100-Hz square
wave, verify that the waveform at the input to the totalizer counter (A1TP20) is delayed
by 1.75 milliseconds from the waveform at A1U8-1.
5A-18. Display Assembly Troubleshooting.
The following discussion is helpful if it has been determined that the Display Assembly
is faulty. Refer to Figure 5A-8 for Display PCA test points. This initial determination
may not be arrived at easily, since an improperly operating display may be the result of a
hardware or software problem that is not a direct functional part of the Display
Assembly. Consult the General Troubleshooting Procedures found earlier in this section
for procedures to isolate the fault to the Display Assembly. Use the following discussion
of display software operation when troubleshooting problems within a known faulty
Display Assembly. A Display Extender Cable (PN 867952) is available for use during
troubleshooting. Note that this cable must be twisted to mate correctly to the connectors
on Display and Main PCAs.
The Display Controller reads the DTEST* and LTE* inputs to determine how to
initialize the display memory. DTEST* (A2TP4) and LTE* (A2TP5) default to logic 1
and logic 0, respectively, to cause all display segments to be initialized to "on."Either
test point can be jumpered to VCC (A2TP6) or GND (A2TP3) to select other display
initialization patterns. Display Test Patterns #1 and #2 are a mixture of "on" and "off"
segments with a recognizable pattern to aid in troubleshooting problems involving
individual display segments. When either of the special display patterns is selected, the
beeper is also sounded for testing without interaction with the Microprocessor. Table
5A-8 indicates the display initialization possibilities.
Figure 5A-9 shows the timing of communications between the Microprocessor and the
Display Controller. Figures 5A-10 and 5A-11 show Display Test Patterns #1 and #2,
respectively. Refer to the Display Assembly schematic diagram in Section 8 for
information on grid and anode assignments.
When a Hydra display is initially powered up, all display segments should come on
automatically. If this display does not appear, proceed with the following steps: