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1TIDevicesSupportedByThisDocument...............................................................................20
2RegistersCheckedforMulticastDeviceID..............................................................................21
3PacketTypes...............................................................................................................25
4PinDescription..............................................................................................................26
5SERDESMacroConfigurationRegister0(SERDES_CFG0_CNTL)FieldDescriptions.........................29
6LineRateversusPLLOutputClockFrequency........................................................................30
7EffectoftheRATEBits....................................................................................................30
8FrequencyRangeversusMPYValue...................................................................................30
9SERDESReceiveChannelConfigurationRegistern(SERDES_CFGRXn_CNTL)FieldDescriptions........31
10EQBits.......................................................................................................................33
11SERDESTransmitChannelConfigurationRegistern(SERDES_CFGTXn_CNTL)FieldDescriptions........33
12DEBitsofSERDES_CFGTXn_CNTL...................................................................................34
13SWINGBitsofSERDES_CFGTXn_CNTL..............................................................................35
14LSUControl/CommandRegisterFields.................................................................................36
15LSUStatusRegisterFields...............................................................................................37
16RXDMAStateHeadDescriptorPointer(HDP)(AddressOffset600h–63Ch).....................................46
17RXDMAStateCompletionPointer(CP)(AddressOffset680h–6BCh)............................................46
18RXBufferDescriptorFieldDescriptions.................................................................................47
19TXDMAStateHeadDescriptorPointer(HDP)(AddressOffset500h–53Ch).....................................51
20TXDMAStateCompletionPointer(CP)(AddressOffset58h–5BCh)..............................................52
21TXBufferDescriptorFieldDefinitions...................................................................................52
22WeightedRoundRobinProgrammingRegisters(AddressOffset7E0h–7ECh)...................................56
23ExamplesofDOORBELL_INFODesignations(SeeFigure26).....................................................64
24FlowControlTableEntryRegistern(FLOW_CNTLn)FieldDescriptions..........................................67
25FieldsWithinEachFlowMask............................................................................................68
26ResetHierarchy............................................................................................................70
27GlobalEnableandGlobalEnableStatusFieldDescriptions.........................................................72
28BlockEnableandBlockEnableStatusFieldDescriptions...........................................................73
29PeripheralControlRegister(PCR)FieldDescriptions.................................................................74
30PortModeRegisterSettings..............................................................................................77
31MulticastDeviceIDOperation.............................................................................................81
32PacketForwardingRegisternfor16-BitDeviceIDs(PF_16B_CNTLn)FieldDescriptions......................81
33PacketForwardingRegisternfor8-BitDeviceIDs(PF_8B_CNTLn)FieldDescriptions.........................82
34Logical/TransportLayerErrorDetectCSR(ERR_DET)FieldDescriptions........................................83
35InterruptConditionStatusandClearBits...............................................................................87
36InterruptConditionsShowninLSU_ICSRandClearedWithLSU_ICCR..........................................90
37InterruptConditionsShowninERR_RST_EVNT_ICSRandClearedWithERR_RST_EVNT_ICCR..........91
38InterruptClearingSequenceforSpecialEventInterrupts............................................................92
39InterruptConditionRoutingOptions.....................................................................................93
40SerialRapidIO(SRIO)Registers.......................................................................................102
41PeripheralIDRegister(PID)FieldDescriptions......................................................................111
42PeripheralControlRegister(PCR)FieldDescriptions...............................................................112
43PeripheralSettingsControlRegister(PER_SET_CNTL)FieldDescriptions.....................................113
44PeripheralGlobalEnableRegister(GBL_EN)FieldDescriptions..................................................116
45PeripheralGlobalEnableStatusRegister(GBL_EN_STAT)FieldDescriptions.................................117
46BlocknEnableRegistersandtheAssociatedBlocks...............................................................119
47BlocknEnableRegister(BLKn_EN)FieldDescriptions.............................................................119
48BlocknEnableStatusRegistersandtheAssociatedBlocks.......................................................120
49BlocknEnableStatusRegister(BLKn_EN_STAT)FieldDescriptions............................................120
10ListofTablesSPRUE13A–September2006
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