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2.3.13InitializationExample
2.3.13.1EnablingtheSRIOPeripheral
2.3.13.2PLL,Ports,DeviceIDandDataRateInitializations
SRIOFunctionalDescription
Formulti-segmentmessages,ifthetransferisunsuccessfulafter256timesofcreditrequestforthefirst
segment,theTXUmovestothenextqueueintheround-robinloop.TheTXUtriestosendtheunsent
messageagainthenexttimearoundtheloop.Afterthefirstsegmentisgrantedoutboundcreditandis
senttothephysicallayerfortransmission,allsubsequentsegmentsaregiven64Kattemptstogain
outboundcredit.IftheTXUisunsuccessfulafterthe64Kattempts,acompletioncodeof111biswrittento
thebufferdescriptor,andthemessageiscancelledwithnoattempttoresend.
Whenthedeviceispoweredon,theSRIOperipheralisinadisabledstate.BeforeanySRIOspecific
initializationcantakeplace,theperipheralneedstobeenabled;otherwise,itsregisterscannotbewritten,
andthereadswillallreturnavalueofzero.
/*Glbenablesrio*/
SRIO_REGS->GBL_EN=0x00000001;
SRIO_REGS->BLK0_EN=0x00000001;//MMR_EN
SRIO_REGS->BLK5_EN=0x00000001;//PORT0_EN
SRIO_REGS->BLK1_EN=0x00000001;//LSU_EN
SRIO_REGS->BLK2_EN=0x00000001;//MAU_EN
SRIO_REGS->BLK3_EN=0x00000001;//TXU_EN
SRIO_REGS->BLK4_EN=0x00000001;//RXU_EN
SRIO_REGS->BLK6_EN=0x00000001;//PORT1_EN
SRIO_REGS->BLK7_EN=0x00000001;//PORT2_EN
SRIO_REGS->BLK8_EN=0x00000001;//PORT3_EN
Tochangefrom1laneto4lanesthereare2registersthatneedtobeprogrammed.SeeTable30.
Table30.PortModeRegisterSettings
DeviceSP_IP_MODE(offset0x12004)PER_SET_CNTL(offset0x0020)PortMode
Bits31-30Bit8
TMS320TCI64820x000x001x/4p
TMS320TCI64820x010x011x/1x
Forexample,EnablePLL,333MHz,1x/4p(srio4p1x_mode=1),x20,125MHzref.clock,2.5Gbps,half
rate:
if(srio4p1x_mode){
rdata=SRIO_REGS->PER_SET_CNTL;
wdata=0x0000014F;//4p1x
mask=0x000001FF;
mdata=(wdata&mask)|(rdata&~mask);
SRIO_REGS->PER_SET_CNTL=mdata;//enablePLL
}
else{
wdata=0x0000004F;//enablePLL,1p4x
rdata=SRIO_REGS->PER_SET_CNTL;
mask=0x000001FF;
mdata=(wdata&mask)|(rdata&~mask);
SRIO_REGS->PER_SET_CNTL=mdata;//enablePLL,1p1x/4x
}
//INIT_MAC0
if(srio4p1x_mode){
SRIO_REGS->SP_IP_MODE=0x4400003F;//Jadismltc/rst/pwenable,clear
}
else{
SRIO_REGS->SP_IP_MODE=0x0400003F;//Jadismltc/rst/pwenable,clear
}
SPRUE13A–September2006SerialRapidIO(SRIO)77
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