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2.3.14BootloadCapability
2.3.14.1ConfigurationandOperation
SRIOFunctionalDescription
SRIO_REGS->SP_RT_CTL=0xFFFFFF00;//long
SRIO_REGS->SP_GEN_CTL=0x40000000;//agent,master,undiscovered
SRIO_REGS->SP0_CTL=0x00600000;//enablei/o
SRIO_REGS->SP1_CTL=0x00600000;//enablei/o
SRIO_REGS->SP2_CTL=0x00600000;//enablei/o
SRIO_REGS->SP3_CTL=0x00600000;//enablei/o
SRIO_REGS->ERR_DET=0x00000000;//clear
SRIO_REGS->ERR_EN=0x00000000;//disable
SRIO_REGS->H_ADDR_CAPT=0x00000000;//clear
SRIO_REGS->ADDR_CAPT=0x00000000;//clear
SRIO_REGS->ID_CAPT=0x00000000;//clear
SRIO_REGS->CTRL_CAPT=0x00000000;//clear
SRIO_REGS->SP_IP_PW_IN_CAPT0=0x00000000;//clear
SRIO_REGS->SP_IP_PW_IN_CAPT1=0x00000000;//clear
SRIO_REGS->SP_IP_PW_IN_CAPT2=0x00000000;//clear
SRIO_REGS->SP_IP_PW_IN_CAPT3=0x00000000;//clear
//INIT_WAITwaitforlaneinitialization
Readregistertocheckportx(1-4)OKbit
//pollingSRIO_MAC'sport_okbit
rdata=SRIO_REGS->P0_ERR_STAT;
while((rdata&0x00000002)!=0x00000002)
{
rdata=SRIO_REGS->P0_ERR_STAT;
}
if(srio4p1x_mode){
rdata=SRIO_REGS->P1_ERR_STAT;
while((rdata&0x00000002)!=0x00000002)
{
rdata=SRIO_REGS->P1_ERR_STAT;
}
rdata=SRIO_REGS->P2_ERR_STAT;
while((rdata&0x00000002)!=0x00000002)
{
rdata=SRIO_REGS->P2_ERR_STAT;
}
rdata=SRIO_REGS->P3_ERR_STAT;
while((rdata&0x00000002)!=0x00000002)
{
rdata=SRIO_REGS->P3_ERR_STAT;
}
}
AssertthePERENbittoenablelogicallayerdataflow
SRIO_REGS->PCR=0x00000004;//peren
Figure41illustratesthesystemcomponentsinvolvedinbootloadoperation.Itisassumedthatanexternal
devicewillinitiatethebootloaddatatransferandmastertheDMAinterface.Uponreset,thefollowing
sequenceofeventsmustoccur:
1.DSPisplacedinSRIObootmodebyHWmodepins.
2.HosttakesDSPoutofreset(PORorRST).Theperipheral’sstatemachinesandregistersarereset.
3.Internalboot-strapROMconfiguresdeviceregisters,includingSERDES,andDMA.DSPexecutes
internalROMcodetoinitializeSRIO.
•Choiceof4pinselectableconfigurations
•Optionally,I2CbootcanbeusedtoconfigureSRIO
SPRUE13A–September2006SerialRapidIO(SRIO)79
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