Filter
Top Products
www.ti.com
5.73PortControlCSRn(SPn_CTL)
SRIORegisters
Eachofthefourportsissupportedbyaregisterofthistype(seeTable148).TheportcontrolCSRn
(SPn_CTL)isshowninFigure136anddescribedinTable149.Tochangefrom1laneto4lanesthere
are2registersthatneedtobeprogrammed.TheSP_IP_MODE(offset0x12004)bits31-30aresettobe
1x/4por4ports(1xmodeeach).ThePER_SET_CNTL(offset0x0020)bit8issetupforport(1x/4p)or
prioritybased(1xmodeeach).
Table148.SPn_CTLRegistersandtheAssociatedPorts
RegisterAddressOffsetAssociatedPort
SP0_CTL115ChPort0
SP1_CTL117ChPort1
SP2_CTL119ChPort2
SP3_CTL11BChPort3
Figure136.PortControlCSRn(SPn_CTL)
313029272624
PORT_WIDTHINITIALIZED_PORT_WIDTHPORT_WIDTH_OVERRIDE
R-01R-000R/W-000
23222120191816
OUTPUT_INPUT_ERROR_
PORT_MULTICAST_
PORT_PORT_CHECK_Reserved
DISABLEPARTICIPANT
ENABLEENABLEDISABLE
R/W-0R/W-0R/W-0R/W-0R-0R-0
158
Reserved
R-0
743210
STOP_PORT_DROP_
PORT_
ReservedFLD_ENC_PACKET_PORT_TYPE
LOCKOUT
ENABLEENABLE
R-0R/W-0R/W-0R/W-0R-1
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table149.PortControlCSRn(SPn_CTL)FieldDescriptions
BitFieldValueDescription
31–30PORT_WIDTHPortwidth.Thisread-onlyfieldindicatesthehardwarewidthof
theport.
00bSingle-laneport(validforallports)
01bFour-laneport(validforport0only)
1xbReserved
29–27INITIALIZED_PORT_WIDTHInitializedportwidth.Thisread-onlyfieldindicatesthewidthof
theportsafterinitialization.
000bSingle-laneport,lane0
001bSingle-laneport,lane2(SeeRapidIOSerialSpec1.2,Chapter
4.4.10)
010bFour-laneport
011b–111bReserved
206SerialRapidIO(SRIO)SPRUE13A–September2006
SubmitDocumentationFeedback