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5.68PortGeneralControlCSR(SP_GEN_CTL)
SRIORegisters
TheportgeneralcontrolCSR(SP_GEN_CTL)isshowninFigure131anddescribedinTable139.
Figure131.PortGeneralControlCSR(SP_GEN_CTL)-AddressOffset113Ch
313029280
MASTER_
HOSTDISCOVEREDReserved
ENABLE
R/W-0R/W-0R/W-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table139.PortGeneralControlCSR(SP_GEN_CTL)FieldDescriptions
BitFieldValueDescription
31HOSTAhostdeviceisadevicethatisresponsibleforsystemexploration,initialization,
andmaintenance.AgentorslavedevicesaretypicallyinitializedbyHost
devices.
0AgentorSlavedevice
1Hostdevice
30MASTER_ENABLETheMasterEnablebitcontrolswhetherornotadeviceisallowedtoissue
requestsintothesystem.IftheMasterEnableisnotset,thedevicemayonly
respondtorequests.
0Processingelementcannotissuerequests
1Processingelementcanissuerequests
29DISCOVEREDThisdevicehasbeenlocatedbytheprocessingelementresponsibleforsystem
configuration.
0Thedevicehasnotbeenpreviouslydiscovered
1Thedevicehasbeendiscoveredbyanotherprocessingelement
28–0Reserved0Theseread-onlybitsreturn0swhenread.
SPRUE13A–September2006SerialRapidIO(SRIO)199
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