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5.96PortControlIndependentRegistern(SPn_CTL_INDEP)
SRIORegisters
Eachofthefourportsissupportedbyaregisterofthistype(seeTable182).Theportcontrolindependent
registern(SPn_CTL_INDEP)isshowninFigure159anddescribedinTable183.
Table182.SPn_CTL_INDEPRegistersandtheAssociatedPorts
RegisterAddressOffsetAssociatedPort
SP0_CTL_INDEP14004hPort0
SP1_CTL_INDEP14104hPort1
SP2_CTL_INDEP14204hPort2
SP3_CTL_INDEP14304hPort3
Figure159.PortControlIndependentRegistern(SPn_CTL_INDEP)
3130292827262524
ReservedTX_FLWSOFT_RECReservedFORCE_REINITTRANS_MODE
R-0R/W-0R/W-0R-0W-0R/W-01
2322212019181716
SEND_DBG_ILL_TRANS_ILL_TRANS_MAX_RETRY_MAX_RETRY_
DEBUGReserved
PKTENERRENERR
R/W-0R/W-0R/W-0R/W-0R-0R/W-0R/W-0
158
MAX_RETRY_THR
R/W-00h
7650
IRQ_ENIRQ_ERRReserved
R/W-0R/W-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
Table183.PortControlIndependentRegistern(SPn_CTL_INDEP)FieldDescriptions
BitFieldValueDescription
31Reserved0Thisread-onlybitreturns0whenread.
30TX_FLWTransmitLinkFlowControlenable
0Disablestransmitflowcontrol(Enablesreceivelinkflowcontrol)
1Reserved
29SOFT_RECSoftwarecontrollederrorrecovery
0Transmissionoferrorrecoverysequenceisperformedbythehardware
1Transmissionoferrorrecoverysequenceisperformedbythesoftware.By
defaultthetransmissionerrorrecoverysequenceisperformedbythehardware.
Ifthisbitisset,thehardwarerecoveryisdisabledandthehardware
transmissionlogicmustwaituntilsoftwarehaswrittentheregisterPortnLocal
ackIDStatusCSR.
28–27Reserved0Theseread-onlybitsreturn0swhenread.
26FORCE_REINITForcereinitializationprocess.In4xmodethisbitaffectsall4lanes.Thisbitis
writeonly,andreadsalwaysreturn0.
25–24TRANS_MODEDescribesthetransfermodeforeachport.
00bReserved(Cut-ThroughMode)
01bStore&ForwardMode
1xbReserved
236SerialRapidIO(SRIO)SPRUE13A–September2006
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