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2.3.2SERDESMacroanditsConfigurations
2.3.2.1EnablingthePLL
SRIOFunctionalDescription
SRIOoffersmanybenefitstocustomersbyallowingascalablenon-proprietaryinterface.Withtheuseof
TI’sSERDESmacros,theperipheralisveryadaptableandbandwidthscalable.Thesameperipheralcan
beusedforallthreefrequencynodesspecifiedinV1.2oftheRapidIOInterconnectSpecification(1.25,
2.5,and3.125Gbps).Thisallowsyoutodesigntoonlyoneprotocolthroughoutthesystemand
selectivelychoosethebandwidth,thuseliminatingtheneedforuser’sproprietaryprotocolsinmany
instances,andprovidingafasterdesignturnandproductionramp.Sincethisinterfaceisserial,the
applicationspaceisnotlimitedtoasingleboard.Itwillpropagateintobackplaneapplicationsaswell.
IntegrationofthesemacrosonanASICorDSPallowsyoutoreducethenumberofdiscretecomponents
ontheboardandeliminatestheneedforbusdriverchips.
Additionally,therearesomevaluablefeaturesbuiltintoTISERDES.Systemoptimizationcanbeuniquely
managedtomeetindividualcustomerapplications.Forexample,controlregisterswithintheSERDES
allowyoutoadjusttheTXdifferentialoutputvoltage(Vod)onaperdriverbasis.Thisallowspower
savingsonshorttracelinks(onthesameboard)byreducingtheTXswing.Similarly,dataedgeratescan
beadjustedthroughthecontrolregisterstohelpreduceanyEMIaffects.Unusedlinkscanbeindividually
powereddownwithoutaffectingtheworkinglinks.
TheSERDESmacroisaself-containedmacrowhichincludestransmitter(TX),receiver(RX),
phase-locked-loop(PLL),clockrecovery,serial-to-parallel(S2P),andparallel-to-serial(P2S)blocks.The
internalPLLmultipliesauser-suppliedreferenceclock.AllloopfiltercomponentsofthePLLareonchip.
Likewise,thedifferentialTXandRXbufferscontainon-chipterminationresistors.Theonlyoff-chip
componentrequirementisforDCblockingcapacitors.
ThePhysicallayerSERDEShasabuilt-inPLL,whichisusedfortheclockrecoverycircuitry.ThePLLis
responsibleforclockmultiplicationofaslowspeedreferenceclock.Thisreferenceclockhasnotiming
relationshiptotheserialdataandisasynchronoustoanyCPUsystemclock.Themultipliedhigh-speed
clockisonlyroutedwithintheSERDESblock;itisnotdistributedtotheremainingblocksoftheperipheral,
norisitaboundarysignaltothecoreofthedevice.Itisextremelyimportanttohaveagoodquality
referenceclock,andtoisolateitandthePLLfromallnoisesources.SinceRapidIOrequires8-bit/10-bit
encodeddata,the8-bitmodeoftheSERDESPLLisnotbeused.
TheSERDESmacroisconfiguredwiththeregisterSERDES_CFG0_CNTL,SERDES_CFGRXn_CNTL,
andSERDES_CFGTXn_CNTL,wherenisthenumberofthemacro.ToenabletheinternalPLL,the
ENPLLbitofSERDES_CFG0_CNTL(seeFigure9andTable5)mustbeset.Aftersettingthisbit,itis
necessarytoallow1µsfortheregulatortostabilize.Thereafter,thePLLwilltakenolongerthan200
referenceclockcyclestolocktotherequiredfrequency,providedRIOCLKandRIOCLKarestable.
RegistersSERDES_CFG1_CNTL,SERDES_CFG2_CNTL,andSERDES_CFG3_CNTLarenotused.
Figure9.SERDESMacroConfigurationRegister0(SERDES_CFG0_CNTL)
3116
Reserved
R-0000h
15109876510
ReservedLBReservedMPYENPLL
R-00hR/W-0R-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=Valueafterreset
SerialRapidIO(SRIO) 28SPRUE13A–September2006
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