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1.3Standards
1.4ExternalDevicesRequirements
1.5TIDevicesSupportedByThisDocument
Overview
FeaturesNotSupported:
•CompliancewiththeGlobalSharedMemoryspecification(GSM)
•8/16LP-LVDScompatible
•DestinationsupportofRapidIOAtomicOperations
•Simultaneousmixingoffrequenciesbetween1xports(allportsmustbethesamefrequency)
•Targetatomicoperations(includingincrement,decrement,test-and-swap,set,andclear)forinternal
L2memoryandregisters
TheSRIOperipheraliscomplianttoV1.2oftheRapidIOInterconnectSpecificationandV1.2ofthe
RapidIOPhysicalLayer1x/4xLP-SerialSpecification.Theseandthevariousassociateddocumentslisted
hereincanbefoundattheofficialRapidIOwebsite:www.RapidIO.org.
SRIOprovidesaseamlessinterfacetoalldeviceswhicharecomplianttoV1.2oftheRapidIOPhysical
Layer1x/4xLP-SerialSpecification.ThisincludesASIC,microprocessor,DSP,andswitchfabricdevices
frommultiplevendors.Compliancetothespecificationcanbeverifiedwithbus-functionalmodelsavailable
throughtheRapidIOTradeAssociation,aswellastestsuitescurrentlyavailableforlicensing.
Table1.TIDevicesSupportedByThisDocument
NumberofNumberofNumberofSRIOModule
DeviceDSPCores(CPUs)PortsLanesConfigurationsFrequency
TMS320TCI64821441x/4x,1x/1xDSPfrequency÷4
SerialRapidIO(SRIO) 20SPRUE13A–September2006
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